Built-in libraries for Universal Verification Methodology.
One of the most useful features in version 10.7c is the ability to manually drive signals during a debug session. Instead of rewiring your testbench, you can right-click a signal in the and force a value. questasim 10.7c download
: Advanced verification capabilities including UVM (Universal Verification Methodology) support, Power Aware simulation (UPF), and high-capacity formal verification integration. Important Security & Legal Warning Built-in libraries for Universal Verification Methodology
: Full compatibility with Verilog, SystemVerilog, VHDL, and SystemC. Power Aware simulation (UPF)